The present invention relates to a semiconductor integrated circuit and method of forming the same, and more particularly to a reference type input first stage circuit in a semiconductor integrated circuit and a method of forming the same.
In recent years, the requirement for improvement in high speed performance of the semiconductor memory device has been on the increase. In response to the above requirement, a reference type input first stage circuit has been used in place of an invertor type first stage circuit. The reference type input first stage circuit is capable of shortening an operating time by about 1 nanosecond as compared to the invertor type first stage circuit.
FIG. 1 is a circuit diagram illustrative of a first conventional reference type first stage circuit. The first conventional reference type first stage circuit comprises first and second invertor circuits. The first invertor circuit comprises a series connection of a first transistor Q31 and a third transistor Q33 between a high voltage line and a ground line. The first transistor Q31 is connected to the high voltage line, whilst the third transistor Q33 is connected to the ground line. The second invertor circuit also comprises a series connection of a second transistor Q32 and a fourth transistor Q34 between the high voltage line and the ground line. The second transistor Q32 is connected to the high voltage line, whilst the fourth transistor Q34 is connected to the ground line. The first conventional reference type first stage circuit also has a reference voltage input terminal InR3 which is connected to a gate of the third transistor Q33 as well as a signal input terminal In3 which is connected to a gate of the fourth transistor Q34. Gates of the first and second transistors Q31 and Q32 are connected in series to each other through a first node. A gate of the first transistor Q31 is connected to a gate of the second transistor Q32 through a second node. The first node is also connected to the second node. The second and fourth transistors Q32 and Q34 are connected in series to each other through an output node which is connected to an output terminal Out3. The first and second transistors Q31 and Q32 comprise p-channel MOS field effect transistors, whilst the third and fourth transistors Q33 and Q34 comprise n-channel MOS field effect transistors.
The above reference type input first stage circuit has the following advantages as compared to the invertor type input first stage circuit. The first advantage is that the reference type input first stage circuit is superior in high speed performance as compared to the invertor type input first stage circuit. The second advantage is that it is easy to change a first stage characteristic (VIH/VIL) by changing a reference voltage level Vref as inputted into the reference voltage input terminal, wherein "VIH" means a point where the output node connected to the next stage is changed from high level to low level upon sensing of the high level by the first stage when the input signal is changed in level from the low level to the high level, whilst "VIL" means a point where the output node connected to the next stage is changed from low level to high level upon sensing of the low level by the first stage when the input signal is changed in level from the high level to the low level.
The reference type input first stage circuit superior in high speed performances is so sensitive that the first stage characteristic (VIH/VIL) is variable by influences of noises or level shift on a power voltage level Vdd and a ground level. Those level shifts depend upon actual layouts, for example, distances from individual pads, and influences by operations of other circuit near the first stage circuit.
FIG. 2 is a circuit diagram illustrative of a conventional circuit comprising first and second reference type input first stage circuits "A" and "B". The first reference type first stage circuit "A" comprises first and second invertor circuits. The first invertor circuit comprises a series connection of a first transistor Q41 and a third transistor Q43 between a high voltage line and a ground pad 6. The first transistor Q41 is connected to the high voltage line, whilst the third transistor Q43 is connected through a first ground pad resistance Rg1 to the ground pad 6. The second invertor circuit also comprises a series connection of a second transistor Q42 and a fourth transistor Q44 between the high voltage line and the ground line. The second transistor Q42 is connected to the high voltage line, whilst the fourth transistor Q44 is connected through the first ground pad resistance Rg1 to the ground pad 6. The first reference type first stage circuit is connected to a reference voltage generating circuit 1 which is connected through a series connection of first and second resistances R11 and R12 to the ground line. An intermediate point between the first and second resistances R11 and R12 is connected to a gate of the third transistor Q43 for applying a reference voltage Vref to the gate of the third transistor Q43. The first reference type input first stage circuit has a signal input terminal In1 which is connected to a gate of the fourth transistor Q44. Gates of the first and second transistors Q41 and Q42 are connected in series to each other through a first node. A gate of the first transistor Q41 is connected to a gate of the second transistor Q42 through a second node. The first node is also connected to the second node. The second and fourth transistors Q42 and Q44 are connected in series to each other through an output node which is connected to an output terminal Out1. The first and second transistors Q41 and Q42 comprise p-channel MOS field effect transistors, whilst the third and fourth transistors Q43 and Q44 comprise n-channel MOS field effect transistors.
The second reference type first stage circuit "B" comprises first and second invertor circuits. The first invertor circuit comprises a series connection of a first transistor Q51 and a third transistor Q53 between a high voltage line and the ground pad 6. The first transistor Q51 is connected to the high voltage line, whilst the third transistor Q53 is connected through the first ground pad resistance Rg1 and a second ground pad resistance Rg2 to the ground pad 6. The second invertor circuit also comprises a series connection of a second transistor Q52 and a fourth transistor Q54 between the high voltage line and the ground pad 6. The second transistor Q52 is connected to the high voltage line, whilst the fourth transistor Q54 is connected through the first ground pad resistance Rg1 and the second ground pad resistance Rg2 to the ground pad 6. The second reference type first stage circuit is also connected to the reference voltage generating circuit 1 which is connected through the series connection of the first and second resistances R11 and R12 to the ground line. The intermediate point between the first and second resistances R11 and R12 is connected to a gate of the third transistor Q53 for applying a reference voltage Vref to the gate of the third transistor Q53. The reference type input first stage circuit has a signal input terminal In2 which is connected to a gate of the fourth transistor Q54. Gates of the first and second transistors Q51 and Q52 are connected in series to each other through a first node. A gate of the first transistor Q51 is connected to a gate of the second transistor Q52 through a second node. The first node is also connected to the second node. The second and fourth transistors Q52 and Q54 are connected in series to each other through an output node which is connected to an output terminal Out2. The first and second transistors Q51 and Q52 comprise p-channel MOS field effect transistors, whilst the third and fourth transistors Q53 and Q54 comprise n-channel MOS field effect transistors.
The mechanism of the ground level shift will e described with reference to the circuit shown in FIG. 2. The first reference type input first stage circuit "A" is positioned closer to the ground pad 6 than the second reference type input first stage circuit "B". The first reference type input first stage circuit "A" is connected to the ground pad 6 but only through the first ground pad resistance Rg1, whilst the second reference type input first stage circuit "B" is connected to the ground pad 6 through not only the first ground pad resistance Rg1 but also the second ground pad resistance Rg2. The magnitude of the ground level shift depends upon the total resistance between the reference type input first stage circuit and the ground pad, for which reason the magnitude of the ground level shift on the second reference type input first stage circuit "B" is larger than that of the first reference type input first stage circuit "A". The magnitude of the voltage level shift is influenced by the circuit connected to the ground line and operations thereof. This mechanism is also applied to the power voltage line.
The above reference type first stage circuit capable of showing the high speed performance has a serious problem with variation in the first stage characteristic (VIH/VIL) due to power voltage level shift or ground voltage level shift. This problem with the power voltage level shift or the ground voltage level shift is caused on the layout of the reference type first stage circuits. This possible variation in the first stage characteristic (VIH/VIL) reduces margins to the required specifications or may cause the problem in spec-out. The reference type first stage circuit with the reduced margin to the first stage characteristic (VIH/VIL) may cause other problem with possible malfunction due to slight noises.
It is theoretically possible that simulations are made on design and evaluation processes to conduct previous investigations on noises and shifts of the power voltage level and the ground level, so that reference voltage levels are adjusted with reference to the individual positions of the reference type input first stage circuit. Actually, however, it is difficult to apply the above method to large capacity memory deices such as 16 megabits or 64 megabits. It is difficult for the limited hardware for simulation and for the limited design processes to find worst conditions through simulations in all timings in consideration of all of the memory cells. This difficulty may lead to such a further problem that the worst conditions on the actual products become remarkable on the evaluation process even the worst conditions could not be difficult to be found out. For this reason, it may be necessary to do large scale modification and to the circuit and mask in order to keep the necessary margin.
In the above circumstances, it had been required to develop a novel reference type input first stage circuit and a method of forming the same free from the above problem.